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integrated silicon solution, inc. www.issi.com 1 rev. 00d 03/19/08 copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat- est version of this device specifcation before relying on any published information and before placing orders for products. is43r32800b 8mx32 256mb ddr synchronous dram preliminary information may 2008 description: is43r32800b is a 4-bank x 2,097,152-word x32bit double data rate synchronous dram, with sstl_2 interface. all control and address signals are referenced to the rising edge of clk. input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of clk. the is43r32800b achieves very high speed clock rate up to 200 mhz. it is packaged in 144-ball fbga. features v ? d d /v d d q =2.5v+0.2v (-5, -6, -75) double data rate architecture; two data transfers ? per clock cycle bidirectional, data strobe (dqs) is transmitted/ ? received with data differential clock input (clk and /clk) ? dll aligns dq and dqs transitions with clk ? transitions edges of dqs commands entered on each positive clk edge; ? data and data mask referenced to both edges of ? dqs 4 bank operation controlled by ba0, ba1 (bank ? address) /cas latency C2.0/2.5/3.0 (programmable) ? burst length - 2/4/8 (programmable) ? burst type - sequential/ interleave (program- ? mable) auto precharge / all bank precharge controlled ? by a8 4096 refresh cycles/ 64ms (4 banks concurrent ? refresh) auto refresh and self refresh ? row address a0-11/ column address a0-7, a9- ? sstl_2 interface package 144-ball fbga ? available in industrial temperature ? temperature range: ? commercial (0 o c to +70 o c) industrial (-40 o c to +85 o c) address table parameter 8m x 32 confguration 2m x 32 x 4 banks bank address pins ba0, ba1 autoprecharge pins a8/ap row addresses a0 C a11 column addresses a0 C a7, a9 refresh count 4096 / 64ms key timing parameters parameter -5 -6 -75 unit clk cycle time cas latency = 3 5 6 7.5 ns cas latency = 2.5 5 6 7.5 ns cas latency = 2 7.5 7.5 7.5 ns clk f requency cas latency = 3 200 167 143 mhz cas latency = 2.5 200 167 143 mhz cas latency = 2 143 143 143 mhz access time from clock cas latency = 3 + 0.70 + 0.70 + 0.70 ns cas latency = 2.5 + 0.70 + 0.70 + 0.70 ns cas latency = 2 + 0.75 + 0.75 + 0.70 ns
2 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b /c s/ ras /c as /w ed m0 -3 me mo ry arra y ba nk #0 dq 0- 31 i/ ob uf fe r me mo ry arra y ba nk #1 me mo ry arra y ba nk #2 me mo ry arra y ba nk #3 mo de re gist er co nt ro lc ircu itry addres sb uf fer a0-1 1 ba 0, 1 cl oc kb uf fer co nt ro ls ig na lb uf fer dq sb uf fe r dqs0 -3 dl l clk /clk cke functional block diagram
integrated silicon solution, inc. www.issi.com 3 rev. 00d 03/19/08 is43r32800b cl k, /c lk : ma st er cl oc k ck e: cl oc k en able /c s: ch ip se l ect /ras : ro w address st ro be /cas : co lu mn a dd re ss st ro be /w e: wr ite enab le a0-11 : address inpu t ba 0, 1: ba nk a dd res s inpu t v dd : pow er suppl y v ddq : pow er suppl y fo r ou tp ut vs s: gr ou nd vssq : gr ou nd fo r ou tp ut dq 0-31 : data i/ o dm 0-3 : write mask vref ck e a8 /a p a7 a6 a4 a3 a1 a0 ba 0 nc /c sm nc /c lk cl k nc a5 a9 a1 1 a2 ba 1 nc nc /r asl nc nc vd d vss nc vd d vd d a1 0 vss vd d /w e /c as k dq 8 dq 9 vddq vssq vss vss vss vss vssq vddq dq 23 dq 22 j dq 10 dq 11 vddq vssq vss vss vss vss vssq vddq dq 20 dq 21 h dqs1 dm 1 nc vssq vss vss vss vss vssq nc dm 2 dqs2 g dq 12 dq 13 vddq vssq vss vss vss vss vssq vddq dq 18 dq 19 f dq 14 dq 15 vddq vssq vss vss vss vss vssq vddq dq 16 dq 17 e dq 24 vddq vd d vss vssq vss vss vssq vss vd d vddq dq 7 d dq 25 dq 26 vssq vssq vssq vd d vd d vssq vssq vssq dq 5 dq 6 c dq 27 vddq nc vddq dq 30 vddq vddq dq 1 vddq nc vddq dq 4 b dqs3 dm 3 vssq dq 28 dq 29 dq 31 dq 0 dq 2 dq 3 vssq dm 0 dqs0 a 12 11 10 9 8 7 6 5 4 3 2 1 dq s0-3 : data st ro be v ref : reference voltage pin configuration package code: b 144-ball fbga (top view) (12.00mm x 12.00mm body, 0.8mm ball pitch pin descriptions
4 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b cl k, /clk in put cl oc k: cl ka nd /c lk ar ed if fe re n tia lc lo ck in pu ts .a ll ad dr es sa nd co ntro l in pu ts ig na ls ar es am pl ed on th ec ro ssin go ft he po si ti ve ed ge of cl ka nd ne ga ti ve edgeof /c lk .o ut pu t( re ad )d at ai sr eferen ce dt ot he cr os si ng so f cl ka nd /c lk ( bot hd ir ec tio ns of cr os si ng ). ck ei np ut cl oc ke na bl e: ck ec on tr ol si nt er na lc lo ck .w he nc ke is lo w, in te rnal cl oc k fo rt he fo llow in gc yc le is ce as ed .c ke is al so us ed to sel ect auto /s el fr ef re sh . af te rs el fr ef re sh mo de is star te d, ck eb ec om es as yn ch rono us in pu t. se lf re fr es h is ma in ta in ed as lo ng as ck ei sl ow . /c si np ut ch ip se le ct :w he n/ cs is hi gh ,a ny co mm an dm ea ns no op er at io n. /r as ,/ cas, /w ei np ut co mbin a tio no f/ ra s, /c as ,/ we de fi ne sb as ic co mma nd s. a0-1 1i np ut a0-1 1s pe ci fy th er ow /c ol um na dd re ss in co nj un ct io nw it hb a0 ,1 .t he ro wa ddr es siss pe ci fi ed by a0-11. th ec olum na dd re ss is speci fi ed by a0-7 ,a 9. a8 is al so us ed to in di ca te pr echar ge op ti on .w he na 8i s hi gh at ar ea d/ wr it ec om ma nd ,a na ut op re char ge is pe rfor me d. wh en a8 is hi gh at ap r echar ge co mm an d, al lb anks ar ep r echar ged. ba 0,1 input dq0-3 1 in pu t/o ut pu t dqs0- 3 v dd , vs s powe rs upp ly powe rs upp ly fo rt he memo ry ar ra ya nd pe ri ph eral ci rc u itr y. v ddq ,v ss q powe rs upp ly v ddq an dv ss qa re suppl ie dtot he ou tp ut bu ff er so nl y. ba nk ad dr e ss: ba 0, 1s pe ci fi es on eo ff ou rb anks to wh ic ha co mma nd is appl ie d. ba 0, 1m us tb es et w ith act, pr e, re ad, wr it ec o mma nd s. da ta in put /o utput :d at ab us da ta st ro be :o utput wi th re ad da ta ,i nput wi th wr ite da ta .e dg e- alig ne d w ith re ad da ta ,c en te re dinw ri te da ta .u se dt oc aptu re wr it ed at a. dqs 0f or dq 0- dq7, dqs 1f or dq 8- dq15, dqs2 fo rd q1 6- dq2 3, dqs3 for dq2 4- dq3 1. sy mb ol ty pe descriptio n dm0- 3 in put inpu td at am as k: dm is an input ma sk si gn al fo rw ri te da ta .i np ut da ta is ma sked wh en dm is sa mple dh ig ha lo ng wi th th at in pu td at a dur in ga wr it ea ccess. dm is sa mple do n bot he dge so fd qs . al th ough dm pi ns ar ei np ut on ly ,t he dm lo ad in gm at ch es th ed q and dqs lo ad in g. dm 0f or dq0 - dq7 ,d m1 for dq8 - dq15, dm 2f or dq1 6- dq2 3, dm 3f or dq2 4- dq31 . in pu t/ ou tp ut vr ef input sst l_ 2r eference vo ltage . pin functions
integrated silicon solution, inc. www.issi.com 5 rev. 00d 03/19/08 is43r32800b issi's 256-mbit ddr sdram pr ov id es ba si c fu nc ti on s, bank (r ow ) act iv ate, bu rs t read / wr it e, bank (ro w) precharge ,a nd au to /s el fr ef re sh .e ac hc om ma nd is de fi ne db yc on tr ol si gn al so f/ ra s, /c as an d /w ea tc lk ri si ng ed ge .i na dd itio nt o3s ig na ls ,/ cs ,c ke an da8a re used as ch ip se le ct ,r ef resh op ti on ,a nd precharge op ti on ,r espect iv el y. to know th ed et a ile dd ef init io no fc om ma nd s, pl ea se se et he co mm an dt ru thta bl e. /c s ch ip se le ct :l =s elec t, h= de se le ct /r as co mma nd /c as co mma nd /w e co mma nd ck e re fr es ho p tio n@ re fr es hc om ma nd a8 pr ec harg eo pt io n@ pr ec harg eo rr ea d/ wr it ec om ma nd cl k de fi ne ba si cc om ma nds /c lk activat e( act) [/ra s= l, /c as =/ we =h ] ac tc om ma nd ac ti va te sa ro wi na ni dl eb an ki nd ic ated by ba . read ( r ead) [/ras =h ,/ ca s= l, /w e= h] re ad co mm an ds ta rt sb urst re ad fr om th ea ct iv eb an ki nd ic ated by ba .f ir st ou tp ut da ta appear sa ft er /c as la te ncy. wh en a8 =h at th is co mm an d, th eb an ki sd e act iv ated af te rt he bu rs tr ea d( auto - precharge read a ) wr it e( write) [/ra s= h, /cas =/ we =l ] wr it ec o mma nd st ar ts bu rs tw ri te to th ea ct iv eb an ki nd ic ated by ba .t ot al da ta le ng th to be wr it te n is se tb yb urst le ng th .w he na 8= ha tt hi sc o mma nd ,t he bank is de ac ti va te da ft er th eb urst wr it e (aut o- pr echar ge, writea ) prech ar ge (p re )[ /ras =l ,/ ca s= h, /w e= l] pr ec o mma nd de ac ti va te st he act iv eb an ki nd ic at ed by ba .t hi sc om ma nd al so te rm in ates bu rs tr ea d /w ri te op er at io n. wh en a8 =h at th is co mm an d, al lb an ks ar ed eact iv ated (pr echar ge al l, prea ). auto-ref res h( refa )[ /ras =/ ca s= l, /w e= ck e= h] re fa co mm an ds ta rt sa ut o- re fr es hc yc le .r ef re sh addr es si nc lu di ng bank addr es sa re ge ne ra te d in te rnally .a ft er th is co mma nd ,t he bank sa re prec ha rg ed au to ma ti cal ly . functional description
6 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b h=hi gh le ve l, l=lo wl ev el ,v =v al id ,x =d on 't ca re ,n =clk cy cl en umbe r no te: 1. app lie so nl yt or ea db ur st sw it ha utop r echar ge di sa bl ed ;t hi sc o mma nd is unde fi ne d( an ds ho ul dn ot be us ed )f or re ad bu rs ts wi th au to pr ec harg ee na bl ed ,a nd fo rw r ite bu rsts . 2. ba 0- ba 1s el ec te it he rt he ba se or th ee xt ende dm od er eg iste r( ba 0= 0, ba 1= 0s elec ts mo de re gist er ;b a0 =1 , ba 1= 0s elec ts exte nd ed mo de re gist er ;o th er co mbin at io ns of ba 0-ba 1a re re se rv ed ;a 0-a1 1p r ovi de th e op -c od et ob ew r itte nt ot he sel ected mo de re gist er . command mn em oni c cke n- 1 cke n /c s/ ra s/ ca s/ we ba 0,1 a8 /a p a0-7 , a9-1 1 de se le ct de se lh xhxxx xx x no oper atio n nop hxl hhhxx x ro wa ddr es se nt ry & ba nk ac tiv at e act hhl lh hv vv si ng le ba nk pr ec harg e pr e hhl lh lv lx pr echar ge al lb an ks pr ea hhl lh lh x co lu mn ad dr es se nt ry &w ri te wr ite hhl hl lv lv co lu mn ad dr es se nt ry &w ri te wi th au to -p re ch arge wr itea hhl hl lv hv co lu mn ad dr es se nt ry &r ea d re ad hhl hl hv lv co lu mn ad dr es se nt ry &r ea dw it h au to -pr ech arge re ada hhl hl hv hv au to -ref re sh re fa hhl ll hx xx se lf -r ef re sh entr yr ef sh ll ll hx xx se lf -r ef re sh ex it re fsx lh hx xx xx x lh lh hhxx x bu rs tt er mi nate te rm hhl hh lx xx mo dere gist er se tm rs hhl ll ll lv x no te 1 2 command truth table
integrated silicon solution, inc. www.issi.com 7 rev. 00d 03/19/08 is43r32800b curr en ts tate /c s/ ra s/ ca s/ we ad dr es sc om ma nd ac ti on no te s id le hx xx xd es el no p lh hh xn op no p lh hl ba ter mi lle gal 2 lh lx ba ,c a, a8 re ad /w ri te i lle gal 2 ll hh ba ,r aa ct ba nk ac ti ve ,l at ch ra ll hl ba ,a 8p re /p re an op 4 ll lh xr ef aa ut o- re fr es h ll ll op -c od e, mo de - ad d mr sm od er eg is te rs et 5 5 ro wa ct iv eh xx xx de se ln op lh hh xn op no p lh hl ba ter mi lle ga l lh lh ba ,c a, a8 re ad /r e ada be gi nr ead ,l at ch ca ,d eter mi ne au to -p r echar ge lh ll ba ,c a, a8 wr it e/ wr i tea be gi nw ri te ,l at ch ca ,d et er mi ne au to -p r echar ge ll hh ba ,r aa ct ba nk ac ti ve /i lleg al 2 ll hl ba ,a 8p re /p re ap rechar ge /p r echar ge al l ll lh xr ef ai lle ga l ll ll op -c od e, mo de - ad d mr si lle ga l hx xx xd es el nop (c on ti nue bu rs tt oe nd ) lh hh x nop no p( cont in ue bu rs tt oe nd ) lh hl ba ter mt er mi na te burs t lh lh ba ,c a, a8 re ad /r ea da te rm in at eb ur st ,l at ch ca ,b eg in ne wr ead ,d et er mi ne au to - pr ech ar ge 3 lh ll ba ,c a, a8 wr it e/ wr i tea i lle ga l ll hh ba ,r aa ct ba nk ac ti ve /i lle gal 2 ll hl ba ,a 8p re /p re at er mi na te bu rst, pr ec ha rg e ll lh xr ef ai lle gal ll ll op -c od e, mo de - ad d mr si lle gal re ad(au to - pr echar ge di sa bl ed ) functional truth table
8 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b cu rr en ts tate /c s/ ra s/ ca s/ we ad dr es sc om ma nd ac ti on no te s hx xx xd es el no p( co nt in ue burs tt oe nd ) lh hh xn op no p( co nt in ue burs tt oe nd ) lh hl ba te rm il le gal lh lh ba ,c a, a8 re ad /r e ada te rm in at eb ur st ,l atch ca ,b eg in re ad ,d eter mi ne au to -p r echar ge 3 lh ll ba ,c a, a8 wr it e/ wr it ea te rm in at eb ur st ,l atch ca ,b eg in wr it e, dete rm in ea ut o- prec ha rg e 3 ll hh ba ,r aa ct ba nk acti ve /i lle gal 2 ll hl ba ,a 8p re /p re at er mi na te bu rs t, pr ec ha rg e ll lh xr ef ai ll e gal ll ll op -c od e, mo de - ad d mr si ll e gal hx xx xd es el no p( co nt in ue burs tt oe nd ) lh hh xn op no p( co nt in ue burs tt oe nd ) lh hl ba te rm il le gal lh lh ba ,c a, a8 re ad /r e ada il le gal lh ll ba ,c a, a8 wr it e/ wr it ea il le gal ll hh ba ,r aa ct ba nk acti ve /i lle gal 2 ll hl ba ,a 8p re /p re ap re ch ar ge /i lle gal 2 ll lh xr ef ai ll e gal ll ll op -c ode ,m od e- ad d mr si ll e gal hx xx xd es el nop (c on ti nu eb ur st to en d) lh hh xn op nop (c on ti nu eb ur st to en d) lh hl ba te rm il le gal lh lh ba ,c a, a8 re ad /r e ada il le gal lh ll ba ,c a, a8 wr it e/ wr it ea il le gal ll hh ba ,r aa ct ba nk acti ve /i lle gal 2 ll hl ba ,a 8p re /p re ap re ch ar ge /i lle gal 2 ll lh xr ef ai ll e gal ll ll op -c od e, mo de - ad d mr si ll e gal wr it e( au to - pr ec ha rg e di sa bl ed ) re ad wi th au to -p re char ge wr it ew it h au to -p re char ge function al truth table (continued)
integrated silicon solution, inc. www.issi.com 9 rev. 00d 03/19/08 is43r32800b cu rre nt st at e/ cs /ras /c as /w ea ddr es sc om ma nd ac ti on no te s hx xx xd es el nop (i dl ea ft er tr p) lh hh x nop nop (i dl ea ft er tr p) lh hl ba te rm il leg al 2 lh lx ba ,c a, a8 re ad /w rite il leg al 2 2 ll hh ba ,r aa ct il le ga l ll hl ba ,a 8p re /p re a nop (i dl ea ft er tr p) 4 ll lh xr ef ai l leg al ll ll op -c ode ,m od e- ad d mr si lleg al hx xx xd es el nop (r ow ac ti ve af te rt rc d) lh hh x nop nop (r ow ac ti ve af te rt rc d) lh hl ba te rm il leg al 2 lh lx ba ,c a, a8 re ad /w rite il leg al 2 2 ll hh ba ,r aa ct il le ga l ll hl ba ,a 8p re /p re ai l leg al 2 ll lh xr ef ai lleg al ll ll op -c ode ,m od e- ad d mr si lleg al hx xx xd es el nop lh hh x nop nop lh hl ba te rm il le ga l lh lx ba ,c a, a8 re ad /w rite il le ga l ll hh ba ,r aa ct il le ga l ll hl ba ,a 8p re /p re ai lleg al 2 2 2 2 ll lh xr ef ai lleg al ll ll op -c ode ,m od e- ad d mr si lle ga l ro w ac ti va ti ng wr iter e- covering pr e- c har gi ng functional truth table (continued)
10 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b ab br ev ia ti ons : h= hi gh le ve l, l= lo wl ev el ,x =d on 't ca re ba =b an ka dd re ss ,r a= ro wa ddr ess, ca =c ol um na dd re ss, nop =n oo pe ra tio n no tes : 1. al le nt ri es as su me th at ck ew as hi gh du ri ng th ep re ce ding cl oc kc yc le an dt he cu rr en tc lo ck cy cle. 2. ille gal to ba nk in sp ec ifie ds tate ;f un ct io nm ay be le ga li nt he ba nk in di ca te db yb a, depe nd in go nt he st at eo f th at ba nk . 3. mu st sa ti sf yb us co nt en ti on ,b us tu rn ar ou nd ,w r ite r ec ove ry re qui re me nt s. 4. nop to ba nk pr echar gi ng or in idle st ate. ma yp re ch arge ba nk in di ca te db yb a. 5. ille gal if an yb an ki sn ot id le . ille ga l= de vi ce op er a tio na nd /o rd at a- in te grity ar en ot gu ar an te ed . cu rre nt st at e/ cs /r as /c as /w ea dd re ss co mm an d act ion refreshing hx xx xd es el no p( id le af te rt rc ) lh hh xn op no p( id le af te rt rc ) lh hl ba te rm il le ga l lh lx ba ,c a, a8 read /w ri te il le ga l ll hh ba ,r aa ct il le ga l ll hl ba ,a 8p re /p re a illeg al ll lh xr ef a illeg al ll ll op -c od e, mo de - ad d mr s illeg al hx xx xd es el no p( ro wa ct iv ea ft er tr sc ) lh hh xn op no p( ro wa ct iv ea ft er tr sc ) lh hl ba te rm il le ga l lh lx ba ,c a, a8 read /w ri te il le ga l ll hh ba ,r aa ct il le ga l ll hl ba ,a 8p re /p re a illeg al ll lh xr ef a illeg al ll ll op -c ode ,m od e- ad d mr s illeg al mo de re gi st er se tt in g functional truth table (continued) notes
integrated silicon solution, inc. www.issi.com 11 rev. 00d 03/19/08 is43r32800b ab br ev ia ti ons : h= hi gh le ve l, l= lo wl ev el ,x =d on 't ca re no tes : 1. ck el ow to hi gh tr an s iti on wi ll re -e na bl ec lk an do th er in pu ts as yn ch ro no us ly . am in im um se tu pt im em us tb es a tis fi ed be fo re an yc om ma nd ot he rt ha ne xit. 2. po we r- do wn an ds el f- re fr es hc an be en te re do nl yf ro mt he al lb an ks id le st ate. 3. mu st be le ga lc o mma nd . cu rr en ts ta te ck en -1 ck en /c s/ ra s/ ca s/ we a ddr es sa ct io nn otes hx xx xx xi nv al id 1 lh hx xx xe xi ts el f- re fr es h( id le af te rt rc )1 lh lh hh xe xi ts el f- re fr es h( id le af te rt rc )1 lh lh hl xi ll e gal 1 lh lh lx xi ll e gal 1 lh ll xx xi ll e gal 1 ll xx xx xn op (m ai nt ai ns el f- re fr es h) 1 hx xx xx xi nv al id lh xx xx xe xi tp ow er do wn to id le ll xx xx xn op (m ai nt ai ns el f- re fr es h) hh xx xx xr efer to f unc ti on tr ut ht ab le 2 hl ll lh xe nt er se lf -r ef re sh 2 hl hx xx xe nt er po we rd ow n2 hl lh hh xe nt er po we rd ow n2 hl lh hl xi ll e gal 2 hl lh lx xi ll e gal 2 hl ll xx xi ll eg al 2 lx xx xx xr efer to cu rre nt st at e= po we rd ow n2 hh xx xx xr efer to fu nc ti on tr ut ht ab le hl xx xx xb eg in cl ks us pe nd at ne xt cy cl e3 lh xx xx xe xi tc lk susp en da tn ex tc yc le 3 ll xx xx xm ai nt ai nc lk su sp en d an ys tate ot he rt ha nl is te d a bov e s elf - re fr es hi ng po we r do wn al lb an ks id le cke truth table
12 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b ro w ac ti ve id le pr e ch ar ge powe r dow n re ad re ada wr it e wr it ea powe r on ac t refa refs refsx ckel ckeh mr s ckel ckeh wr it e re ad wr it ea wr it ea re ad a re ad pr e re ad a re ad a pr e pr e prea po we r ap pl ie d mode re gist er se t se lf re fr es h au to re fr es h ac tiv e powe r do wn auto ma ti cs eque nc e co mma nd seque nc e wr it e re ad pr e ch ar ge al l mr s bu rs t st op te rm state diagram
integrated silicon solution, inc. www.issi.com 13 rev. 00d 03/19/08 is43r32800b dc op eratin gc ondition s (t a= 0~ 70 o c mi n. ty p. ma x. s uppl yv ol ta ge 2. 3 2.5 2.5 2. 7 v s uppl yv ol ta ge fo ro utpu t 2. 3 2. 7 v hi gh- le ve li np ut vo lt ag e v ref +0 .1 5v dd +0 .3 v lo w- le ve li nput vo lt ag e -0 .3 v ref -0 .1 5 v i nput l eakag ec ur re nt an yi nput0v 14 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b -5 -6 -7 5 i dd1 op er at in gc u rrent :o ne ba nk ;a ct iv e- re ad -p r ech ar ge ;b ur st =2 ; trc =t rc mi n; tc k= tc km in ;i out =0 ma ;a ddr es sa nd co nt ro l i nput sc hang in go nc ep er cloc kc yc le 250 230 230 i dd5 au to refresh c urrent :t rc =t rf c( mi n) 250 240 240 i dd6 s elf refresh c urrent :c ke < 0. 2v 5 5 5 ac ti ve st a ndb yc urre nt :/ cs > vi h( mi n) ;c ke > vi h( mi n) ; on eb ank; ac ti ve -p r ech ar ge ;t rc =t ra sm ax ;t ck =t ck mi n; dq,dm and dqs in put sc hang in gt wi ce pe rc lo ck cy cl e; a ddr es sa nd ot he r co nt ro li n p ut sc ha n g in g on ce p er cl oc kc y cl e i dd3 n i dd2 p i dd2 n id le st a ndb yc u rrent :/ cs > vi h( mi n) ;a ll bank si dl e; ck e> vi h( mi n) ;t ck =t ck mi n; a ddr es sa nd ot he rc on tr ol in put s ch angi ng on ce pe rc lo ck cy cl e i dd3 p ac ti ve po we r dow ns ta ndb yc urrent :o ne bank ac ti ve ;p ow er do wn mo de ;c ke < vi l( ma x) ;t ck =t ck mi n 360 360 li mi ts(m ax .) 35 100 65 40 35 55 360 no te s sy mb ol pa ra me ter/ te st co nd iti on s ma un it i dd4 w op er at in gc urrent :b ur st =2 ;w r ite ;c on tin uo us bu rst; al lb anks ac tiv e; ad dr es sa nd co nt ro li n put sc hangi ng on ce pe rc lo ck cy cl e; tc k= t ck mi n; dq and dqs in pu ts ch angi ng tw ic ep er cl oc kc yc le pr echa rg ep ow er- dow ns ta ndb yc u rrent :a ll bank si dl e; po we r-d ow nm od e; ck e< vi l( ma x) ;t ck =t ck mi n 400 65 70 105 i dd4 r op er at in gc urrent :b ur st =2 ;r ea d; co nt i nuo us bu rst; al lb anks ac tiv e; ad dr es sa nd co nt ro li np ut sc hang in go nc ep er cl oc kc yc le ;t ck =t ck mi n; i out =0 ma 400 360 100 50 50 v dd = v ddq =2 .5 v+ 0. 2v ,v ss =v ss q= 0v ,o ut pu to pe n, un le ss ot he rw is en ot ed average supply current from v dd
integrated silicon solution, inc. www.issi.com 15 rev. 00d 03/19/08 is43r32800b mi n. ma xm in .m ax mi n. ma x ta cd qo ut pu ta cces st im ef ro mc lk // cl k -0.70 +0 .7 0- 0.70 +0.7 0- 0.75 +0.7 5n s td qs ck dq so ut pu ta cces st im ef ro mc lk // cl k -0. 6+ 0. 6- 0.60 +0.6 0- 0.75 +0.7 5n s tc hc lk hi gh le ve lw id th 0.45 0. 55 0.45 0.55 0.45 0.55 tc k tc lc lk lo wl evel wi dt h 0.4 50 .5 50 .4 50 .5 50 .4 50 .5 5t ck cl =3 .0 57 .5 61 27 .5 12 ns cl =2.5 51261 27 .5 12 ns cl =2.0 7. 51 27 .5 12 7. 51 2n s td si nput se tu pt im e( dq ,d m) 0. 40 .4 50 .5 ns td hi nput ho ld ti me (d q, dm ) 0.4 0.45 0. 5n s ti pw co nt ro l& addr es si nput pu ls ew id th (f or each in pu t) 2. 22 .2 2. 2n s tdip wd qa nd dm in pu tp ul se wi dt h( fo re ac hi nput) 1.7 51 .7 51 .7 5n s th zd at a- ou t- high im peda nc et im ef ro mc lk // cl k +0. 70 +0.7 0+ 0.75 ns 14 tl zd at a- ou t- lo wi mp edance ti me fr om cl k/ /c lk -0 .7 0+ 0. 70 -0 .7 0+ 0.70 -0 .7 5+ 0.75 ns 14 td qs qd qv al id da ta de la yt im ef ro md qs 0. 40 0.45 0. 5n s th pc lo ck ha lf pe ri od tc lm in or tc hm in tc lm in or tc hm in tc lm in or tc hm in ns 20 tq hd qo ut pu th ol dt im ef ro md qs (p er access) th p- tq hs th p- tq hs th p- tq hs ns tq hs data ho ld sk ew fa ct or (f or dq s&a sso ciated dq si gn al s) 0. 50 0.55 0.75 td qs sw ri te co mma nd to fi rs td qs la tc hing tr an si ti on 0.72 1. 25 0.75 1.25 0.75 1.25 tc k td qs hd qs in pu th ig hl evel wi dt h 0.3 50 .3 50 .3 5t ck td qs ld qs in pu tl ow le ve lw id th 0.35 0.35 0.35 tc k td ss dq sf a llin ge dg et oc lk se tu pt im e 0.2 0. 20 .2 tc k td sh dq sf a llin ge dg eh ol dt im ef ro mc lk 0. 20 .2 0. 2t ck tm rd mo de re gi st er se tc o mma nd cycl et ime 222 tc k tw pr es wr it ep re am bl es et up ti me 000 ns 16 tw pst wr it e pos ta mb le 0. 40 .6 0. 40 .6 0. 40 .6 tc k1 5 tw pr ew ri te pr ea mb le 0.25 0.25 0.25 tc k ti si nput se tu pt im e( addr es sa nd co nt ro l) 0. 60 .7 50 .9 ns 19 ti hi nput ho ld ti me (a ddr es sa nd co nt ro l) 0. 60 .7 50 .9 ns 19 tr pst re ad pos ta mb le 0. 40 .6 0. 40 .6 0. 40 .6 tc k tr pr er ea dp re am bl e 0.9 1. 10 .9 1. 10 .9 1. 1t ck tc k sy m bol ac ch arac te ri st ic sp arameter -5 no te s -6 cl kc yc le ti me -7 5 un it ac timing requirements
16 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b outp ut lo ad co nd itio n dq output ti mi ng me as ur emen t re fe re nc ep oi nt v re f v re f dq s v out v re f 30pf 50 v tt =v re f zo =5 0 mi n. ma xm in .m ax mi n. ma x tr as ro wa ct iv et im e 120 ,000 42 40 120,000 45 120, 00 0n s tr cr ow cy cl et im e( oper at io n) 55 60 65 ns tr fc au to re f. to acti ve /a ut or ef .c om ma nd pe ri od 70 72 75 ns tr cd ro wt oc ol um nd elay 15 18 20 ns tr pr ow pr ec ha rg et im e ns t rrd ac tt oa ct de la yt ime ns tw rw ri te r eco ve ry ti me 15 15 15 ns tdal au to pr echar ge wr it er eco ve ry +p r echar ge ti me tw r+ tr pt wr +t rp tw r+ tr pn s tw tr in te rn al wr it et or ead co mm an dd elay 21 1t ck tx sn re xi ts el fr ef .t on on -r ea dc o mma nd 75 75 75 ns tx sr de xi ts el fr ef .t o- re ad co mma nd 200 200 200 tc k tx pn re xi tp ow er dow nt oc om ma nd 11 1t ck tx pr de xi tp ow er dow nt o- r eadco mm an d1 11 tc k1 8 tr ef ia ve ra ge pe ri od ic re fr es hi nt er va l 15.6 15.6 15. 6 - 17 -7 5 un it no te s sy m bol ac ch aracter is ti cs pa ra me te r -5 -6 ( ac timing requirements (continued) 15 18 20 10 12 15 ms w w
integrated silicon solution, inc. www.issi.com 17 rev. 00d 03/19/08 is43r32800b no te s 1. al l vo ltage sr eferenced to vss. 2. te st sf or ac ti mi ng ,i dd, an de l ect ri ca l, ac an dd cc ha ra cter is ti cs ,m ay be co n duc te da tn om in al re fe re nc e/ suppl y vo ltage le ve ls ,b ut th er elated sp eci fi ca tio ns an dd ev ic eo pe ra tio na re gu aran te ed fo rt he fu ll vo ltage ra ng es peci fi ed . 3. ac ti mi ng an di dd te st sm ay us ea vi lt ov ih sw in go fu pt o1 .5 vi nt he te st en vi ro nm en t, bu ti nput timin gi ss till re fe re n ced to vr ef (o rt ot he cr os si ng po in tf or ck // ck), an dp ar am eter sp ec ific atio ns ar e gua ra nt eed fo rt he sp eci fi ed ac in pu tl evel su nd er no rm al us ec on d iti on s. th em inim um sl ew ra te fo rt he i nput si gn al si s1 v/ ns in th e ra nge be tw ee nv il (ac) an dv ih (ac) . 4. th ea ca nd dc in pu tl evel sp ec if ic a tio ns ar ea sd ef in ed in th es st l_ 2s ta nda rd (i .e .t he re ce iv er w ill ef fec tiv el y sw itc ha sa re su lt of th es ig na lc ro ss in gt he ac in pu tl evel ,a nd w ill re ma in in th at st at ea sl on ga st he si gn al do es no t ri ng ba ck a bov e( be lo w) th ed ci np ut lo w( hi gh )l ev el . 5. vr ef is expect ed to be equa lt o0 . 5*vddq of th et ra ns mi ttin gd evice, an dt ot ra ck va ria tio ns in th ed cl evel of th e sa me .p ea k-to -p ea kn oi se on vr ef ma yn ot exceed + 2% of th ed cv alue . 6. vt ti sn ot appl ie dd ir ec tly to th ed ev ic e. vt ti sa syst em su ppl yf or si gn al te rm in a tio nr es isto rs ,i se xp ected to be se te qua lt ov re f, an dm us tt ra ck va ria tio ns in th ed cl evel of vr ef . 7. vi di st he ma gn itu de of th ed i ffe re nc eb et we en th ei np ut le ve lo nc lk an dt he i nput le ve lo n/ cl k. 8. th ev alue of vi xi se xp ected to equa l0 . 5*vdd qo ft he tr an sm itti ng de vi ce an dm us tt ra ck va ria tio ns in th ed cl evel of th es ame. 9. en ab le so n- ch ip re fr es ha nd ad dr es sc ou nt er s. 10. id ds peci fi ca tio ns ar et es te da ft er th ed ev ic ei sp ro pe rl yi ni ti al iz ed . 11. th is pa ra me te ri ss am pl ed .vddq =2 .5 v+ 0. 2v ,vdd =2 .5 v+ 0. 2v ,f = 100 mh z, ta =2 5 o c, vo ut (dc) = vddq /2 ,v ou t( pe ak to pe ak )= 25 mv .d mi np ut sa re gr o upe dw it hi /o pi ns -r ef lectin gt he fa ct th at th ey ar e matc he di nl oa di ng (t of ac ili tate tr ac em atch in ga tt he bo ar dl ev el ). 12. th ec lk// cl ki np ut re fe re nc el evel (f or timin gr eferenced to cl k //c lk )i st he po in ta tw hi ch cl ka nd /c lk cr o ss; th ei nput re fe re nc el evel fo rs ig nals ot he rt ha nc lk// cl k, is vr ef . 13. i nput sa re no tr eco gn iz ed as va lid un ti lv re fs ta b ili ze s. ex ce ptio n: du ri ng th ep er io db ef or ev re fs ta bi li ze s, cke< 0. 3vddq is r eco gn iz ed as low. 14. th za nd tl zt ra ns i tio ns occu ri nt he sa me ac ce ss ti me wi nd ow sasv a lid da ta tr an si tio ns .t he se pa ra me te rs ar en ot re fe re n ced to as pe ci fi cv ol tage le ve l, bu ts pe ci fy wh en th ed ev ic eo utput is no lo ng er dr iv in g( hz ), or be gi ns dr iv in g (lz) . 15. th em ax im um limit fo rt hi sp arameter is no ta de vi ce li mi t. th ed ev ic ew ill op er at ew it ha gr ea te rv al ue fo rt hi s para me te r, bu ts ys te mp er fo rm ance (b us tu rn ar oun d) wi ll degr ad ea cc or di ng ly . 16. th es pe ci fi cr equi re me nt is th at dqs be va li d( hi gh ,l ow ,o ra ts om ep oint on av al id tr an s iti on )o no rb ef or e th is cl ke dge .a va li dt ra ns itio ni sd ef in ed as mo no to ni c, an dm ee tin gt he i nput sl ew ra te sp eci fi ca tio ns of th ed ev ic e. wh en no wr ite sw er ep re viou sl yi np ro gr es so nt he bu s, dq sw il lb et ra ns itio ni ng fr om hi gh -z to lo gi cl ow .i fa pr ev io us wr ite wa si np r ogr ess, dqs co ul db eh ig h, low, or tr an si tio ni ng fr om hi gh to lo wa tt hi st im e, depe nd in go nt dqss. 17. am ax im um of ei gh ta ut or ef re sh co mma nd s can be po st ed to an yg iv en ddr sd ra md ev ic e. 18. tx pr ds ho ul db e 200 tc lk in th ec on di tio no ft he un stab le cl ko pe ra ti on du ri ng th ep ow er do wn mo de . 19. fo rc om ma nd/ ad dr es sa nd ck &/ ck sl ew ra te >1 .0 v/ ns . 20. mi n( tc l, tc h) re fe rs to th es ma lle ro ft he ac tual cl oc kl ow tim ea nd th ea ct ua lc lo ck hi gh tim ea sp ro vi de dt ot he de vi ce. ti mi ng pa tt er ns : tc k= mi n,tr rd = 2*t ck,b l= 4, tr cd=3 *t ck ,r ea dw ith autopr echar ge re ad:a 0n a1 r0 a2 r1 nr 3a0n a1 r 0?r epea tt he sa me ti mi ng wi th ra ndo ma ddr es sc hang in g *100% of data ch anging at ever yb ur st le ge nd :a =a ct iv at e, r= re ad,p =p re ch arge ,n =n op
18 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b functional description the is43r32800b is a 256mb ddr sdram internally configured as a quad--bank dram. these 256mb device contains 4 banks x 2,097,152 x32 bits. the ddr sdram uses a double--dat a--rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr sdram consists of a single 2n-bit wide, one clock cycle data transfer at the inte rnal dram core and tw o corresponding n-bit wide, one-half clock cycle data transfers at the i/o pins. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence . accesses begin with the registration of an active command, which is then followed by a read or write co mmand. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0-a11 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the ddr sdram must be initia lized. the following sections provide detailed information covering device initialization, register definition, comm and descriptions and device operation. initialization ddr sdrams must be powered up and initialized in a predefined manner. power on sequence before starting normal operation, the following power on se quence is necessary to prevent a ddr sdram from damaged or multi functioning. 1. apply vdd before or the same time as vddq 2. apply vddq before or at the same time as vtt & vref 3. maintain stable condition for 200us after stable power and clk, apply nop or dsel 4. issue precharge command for all banks of the device 5. issue emrs 6. issue mrs for the mode register and to reset the dll 7. issue 2 or more auto refresh commands 8. maintain stable condition for 200cycles after these sequence, the dd r sdram is idle state and ready for normal operation.
integrated silicon solution, inc. www.issi.com 19 rev. 00d 03/19/08 is43r32800b /c s /r as /cas /w e a11-a0 /c lk v cl k ba 0 ba 1 r: re se rv ed fo rf ut ur eu se 0n o 1y es dl lr es et 0s eq ue nt ia l 1i nt erl eav ed bu rs tt ype bt =0 bt =1 00 0r r 00 12 2 01 04 4 01 18 8 10 0r r 10 1r r 11 0r r 11 1r r bl bu rs t le ngt h /c as la te nc y 00 0r 00 1r 01 02 01 13 10 0r 10 1r 11 02 .5 11 1r cl late nc y m ode ba 1b a0 a1 1a 10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 00 00 0d r0 bt lt mo de bl mode register definition register definition mode register the mode register is used to define the specific mode of operation of the ddr sdram. this definition includes the selection of a burst length, a burst type, a cas latency, and an operating mode, as shown in figure ?mode register definition?. the mode register is programmed via t he mode register set (mrs) command (with ba0 = 0 and ba1 = 0) and will retain stored information until it is programmed again or t he device loses power. mode register bits a0-a2 specify the burst length, a3 specifie s the type of burst (sequential or interleaved), a4-a6 specify the cas latency, and a7-a11 sp ecify the operating mode. the mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subs equent operation. after tmrd from a mrs command the ddr sdram is ready for a new command. violating either of these requirem ents will result in unspecified operation.
20 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being programmable, as shown in figure ?cas latency?. the burst length determine s the maximum number of column locations that can be accessed for a given read or write command. burst length s of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst w ill wrap within the block if a boundary is reached. the block is uniquely selected by a1--ai when the burst length is set to two, by a2--ai when the burst length is set to four and by a3--ai when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to bot h read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table ?burst definition?. read latency the read latency is the delay, in cl ock cycles, between the registration of a read command and the availability of the first piece of output data. if a read command is regist ered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. reserved states should not be used as unknown oper ation, or incompatibility with future versions may result.
integrated silicon solution, inc. www.issi.com 21 rev. 00d 03/19/08 is43r32800b /cas la te nc y bu rs t le ng th cl =2 bl =4 bu rs t le ng th a2 a1 a0 init ia la dd re ss bl sequen tia l int er le av ed co lu mn ad dr essi ng 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 -0 0 -0 1 -1 0 -1 1 -- 0 01 2345 67 0123 4 567 12 3456701 03 25476 23 4567012 30 16745 34 5670123 21 07654 45 6701234 56 7012 3 56 7012345 47 6103 2 67 0123456 74 5230 1 70 12 01 23 12 30 23 01 30 01 7654 0123 1032 2301 32 01 -- 1 12 10 345 63 21 0 10 10 8 4 2 co mm an d addr es s dq yy read wr it e dqs q0 q1 q2 q3 d0 d1 d2 d3 /c lk cl k cas latency burst definition
22 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b /c s /r as /cas /w e a11-a0 v ba 0 ba 1 /c lk cl k ba 1b a0 a1 1a 10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 01 00 00 00 00 00 ds dd 0n or ma l 1w eak dr iv e st re ngt h 0d ll en ab le 1d ll di sa bl e dl ld is ab le extended mode register extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions include dll enable/disable, ou tput drive strength select ion (optional). these functions are controlled via the bits shown in figure extended mode register. the extended mode register is programmed via the mo de register set command (with ba0 = 1 and ba1 = 0) and will retain the stored information until it is progr ammed again or the device loses power. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. after tmrd fr om a mrs command the ddr sdram is ready for a new command. violating either of these r equirements will result in unspecified operation. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization, and upon returning to normal operation after having disabled the dll for the purpose of debug or evaluation (upon exiting self refresh mode, the dll is enabled automatically). an y time the dll is enabled a dll reset must follow and 200 clock cycles must occu r before any executable command can be issued. output drive strength the normal drive strength for all outputs is specified to be sstl_2, class ii. the issi ddr sdram also supports a weak driver strength option, intended for lighter load and/or point-to-point environments.
integrated silicon solution, inc. www.issi.com 23 rev. 00d 03/19/08 is43r32800b /clk dq s tis tih vref cl k va lid da ta ta c tdqs ck tc l tc h tc k tdqs q tq h tr pr e tr ps t dq s /clk cl k tdqs s td st dh tdqs l tdqs h tw pr e writ eo pe ra tion /t dqss=max. td ss tw pr es tw ps t dq s /clk cl k tdqs s td st dh tdqs lt dq sh tw pr e writ eo pe ra tion /t dqss=min. td sh tw pr es tw ps t dq dq dq cm d& ad d. read operation
24 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b th e ddr sdra mh as fo ur in de pe nd en tb an ks .e ac hb an ki sa ct iv ated by th ea ct co mm an dw it h th eb an ka ddr es se s( ba 0,1) .a ro wi si nd i cated by th er ow addr es sa 0-11. th em in im um act iv at io n in te rval be tw een on eb an ka nd th eo th er bank is tr rd . ba nk activate th ep re co mma nd de act iv ates th eb an ki nd i cated by ba 0,1. wh en mu lt iple ba nk sa re ac ti ve ,t he precharge al lc om ma nd (pre a, pre+ a8 =h )i sa va il ab le to deact iv at et he ma tt he sa me ti me .a ft er tr pf ro mt he prec ha rge, an ac tc o mma nd to th es am eb an kc an be issued . prec harge ba nk activati on an dp re ch ar ge al l( bl =8 ,c l= 2) ap rech arge co mma nd ca nb ei ss ue da tb l/ 2f ro ma read co mm an dw it ho ut da ta lo ss . pr ec harg ea ll co mm an d a0-7 ,9-1 1 a8 ba 0, 1 dq ac t xa xa 00 re ad y 0 00 ac t xb xb 01 pr e tr rd tr cd 1 ac t xb xb 01 tr as tr p tr cm in 2a ct comma nd /t rcmi n dqs qa 0 bl /2 qa 1q a2 qa 3q a4 qa 5q a6 qa 7 /c lk cl k operational description
integrated silicon solution, inc. www.issi.com 25 rev. 00d 03/19/08 is43r32800b af te rt rcd fr om th eb an k act iv at io n, ar ea dc om ma nd ca nb ei ss ued. 1s to ut pu td at ai sa va il ab le af te rt he /c as la te nc yf ro mt he re ad ,f ol lo we db y( bl-1 )c on se cu ti ve da ta wh en th eb ur st le ng th is bl .t he st ar ta ddres si ss pe ci fi ed by a0 -7,9 ,a nd th ea ddres ss eque nc eo fb ur st da ta is de fi ne db y th eb ur st ty pe .a re ad co mma nd ma yb ea pp li ed to an ya ct iv eb an k, so th er ow prec ha rg et im e (t rp ) can be hidde nb eh in dc on ti nu ou so ut pu td at ab yi nt er le av in gt he mu lt iple bank s. wh en a8 is hi gh at ar ea dc o mma nd, th ea ut o- prech arge (rea da )i sp er fo rm ed .a ny co mm an d(re ad ,w ri te,p re ,a ct )t ot he sa me bank is in hibi te dt il lt he in te rn al prec harg ei s co mp le te .t he in te rnal pr ec ha rg es ta rt sa tb l/ 2a ft er re ad a. th en ex ta ct co mm an dc an be is su ed af te r( bl/2+t rp )f ro mt he previ ous re ad a. read mu lt ib an ki nter le avin gr ea d( bl =8 ,c l=2) /c lk co mm an d a0-7 ,9-1 1 a8 ba 0, 1 dq ac t xa xa 00 re ad y 0 00 re ad y 0 10 ac t xb xb 10 pr e 0 00 tr cd /c as late ncy bu rs tl en gt h dqs qa 0 cl k qa 1q a2 qa 3q a4 qa 5q a6 qa 7q b0 qb 1q b2 qb 3q b4 qb 5q b7 qb 8
26 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b tr cd tr p bl /2 bl /2 +t rp read with auto -p rech arge (b l=8, cl=2 ,2.5,3.0) co mma nd a0-7 ,9-1 1 a8 ba 0, 1 dq ac t xa xa 00 re ad y 1 00 dqs /c lk cl k inte rn al pr echar ge st ar tt imin g qa 0q a1 qa 2q a3 qa 4q a5 qa 6q a7 dq dqs qa 0q a1 qa 2q a3 qa 4q a5 qa 6q a7 cl =2 cl =2.5 01 234 56 78 91 01 11 2 dq dq s qa 0q a1 qa 2q a3 qa 4q a5 qa 6q a7 cl =3.0
integrated silicon solution, inc. www.issi.com 27 rev. 00d 03/19/08 is43r32800b af te rt rcd fr om th eb an k act iv at io n, aw ri te co mma nd ca nb ei ss ued. 1s ti n put da ta is se tf ro m th ew ri te co mma nd wi th da ta st ro be in put ,f ol lo wi ng (b l- 1) da ta ar ew ri tt en in to ra m, wh en th eb ur st leng th is bl .t he st ar ta ddres si ss pe ci fied by a0 -7,9 ,a nd th ea ddres ss eque nc eo fb ur st da ta is de fi ne db yt he burs tt yp e. aw ri te co mm an dm ay be ap pl ie dt oa ny ac ti ve bank ,s ot he ro wp r ech arge ti me (t rp )c an be hidde nb eh in dc on ti nu ou si n put da ta by in te rl ea ving th em ul ti pl e bank s. fr om th el as td at at ot he pr ec o mma nd, th ew ri te reco ve ry ti me (t wr p) is requ ir ed .w he n a8 is hi gh at aw ri te co mma nd ,t he auto -prech ar ge(w ri te a) is pe rf or me d. an y co mm an d(re ad ,w ri te,p re ,a ct )t ot he sa me bank is in hibi te dt il lt he in te rn al prec harg ei s co mp le te .t he next ac tc o mma nd ca nb ei ss ue da ft er td al fr om th el as ti n put da ta cy cl e. writ e mu lt ib an ki nter le avin gw rite (b l=8) co mm an d a0-7 ,9-1 1 a8 ba 0, 1 dq ac t xa 00 wr it e 00 wr it e 0 0 10 ac t xb 10 0 10 tr cd d tr cd d pr e xa 0 00 pr e dqs /c lk cl k da 0d a1 da 2d a3 da 4d a5 da 6d a7 db 0d b1 db 2d b3 db 4d b5 db 6d b7 xa ya yb xb
28 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b writ ew it ha ut o-p rech ar ge (b l=8) co mm an d a0-7 ,9-1 1 a8 ba 0, 1 dq ac t xa 00 wr it e 1 00 ac t xb 00 tr c d da 0 dqs /c lk cl k da 1d a2 da 3d a4 da 5d a6 da 7 td al xa y xb 01 23 45 67 89 10 11 12
integrated silicon solution, inc. www.issi.com 29 rev. 00d 03/19/08 is43r32800b r ea di nter ru pted by read burs tr ea do pera ti on ca nb ei nt e rrupt ed by ne wr ea do fa ny bank .r an do mc ol um na cces si sa ll ow ed . re ad to re ad in te rv al is mi ni mu m1 cl k. read int err upted by read (b l=8, cl=2 ) co mma nd a0-7 ,9-1 1 a8 ba 0, 1 dq yi re ad re ad re ad re ad yj yk yl 00 00 00 10 00 01 dqs qa i0 qa i1 qa j0 qa j1 qa j2 qa j3 qa k0 qa k1 qa k2 qa k3 qa k4 qa k5 qa l0 qa l1 qa l2 qa l3 qa l4 qa l5 qa l6 qa l7 /c lk cl k r ea di nter ru pted by pr ech arge burs tr ea do pera ti on ca nb ei nt e rrupt ed by prec harg eo ft he sa me bank .r ea dt op re in te rval is mi ni mu m1 cl k. ap re co mma nd to ou tp ut di sa bl el at ency is eq ui va le nt to th e/ ca sl aten cy . as ar es ul t, re ad to pr ei nt erva ld eter mi ne sv al id da ta le ng th to be ou tp ut .t he fi gur eb el ow sh ow se xa mp le so fb l=8. read int err upted by p rech ar ge (b l=8) cl=2 .0 /c lk cl k co mma nd dqs co mma nd dq co mma nd dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 pr e re ad re ad pr e re ad pr e dqs dqs burst interruption
30 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b read int err upted by p rech ar ge (b l=8) cl=2 .5 co mma nd dqs co mma nd dq co mma nd dq q0 q1 q2 q3 q0 q1 /c lk cl k dq q0 q1 q2 q3 q4 q5 pr e re ad re ad pr e re ad pr e dqs dqs read int err upted by p rech ar ge (b l=8) cl=3 .0 /c lk cl k co mma nd dqs co mma nd dq co mma nd dq dq pr e re ad re ad pr e q0 q1 q2 q3 q4 q5 re ad pr e dqs q0 q1 q2 q3 dqs q0 q1
integrated silicon solution, inc. www.issi.com 31 rev. 00d 03/19/08 is43r32800b burs tr ea do pera ti on ca nb ei nt e rrupt ed by ab ur st st op co mma nd( te rm). re ad to te rm in te rv al is mi ni mu m1 cl k. at er mc o mma nd to ou tp ut di sabl el at ency is eq ui va le nt to th e/ ca sl at ency . as ar es ul t, re ad to te rm in te rv al de te rm in es va li dd at al en gt ht ob eo ut pu t. th ef i gur eb el ow sh ow se xa mp le so fb l=8. r ea di nter ru pted by bu rs ts top read int err upted by ter m( bl =8 ) /c lk cl k cl=2 .5 co mma nd dqs co mma nd dq co mma nd dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 te rm re ad re ad te rm re ad te rm dqs dqs cl=2 .0 co mma nd dqs co mma nd dq co mma nd dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 te rm re ad re ad te rm re ad te rm dqs dqs
32 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b r ea di nter ru pted by wr it ew it ht er m read int err upted by ter m( bl =8 ) /c lk cl k cl=2 .5 co mma nd dq q0 q1 q2 q3 re ad ter m dqs wr it e d0 d1 d2 d3 d4 d5 cl=2 .0 co mma nd dq q0 q1 q2 q3 re ad ter m dqs wr it e d0 d1 d2 d3 d4 d5 d6 d7 read int err upted by ter m( bl =8 ) /c lk cl k cl=3 .0 co mma nd dqs co mma nd dq co mma nd dq dq te rm re ad re ad te rm q0 q1 q2 q3 q4 q5 re ad te rm dqs q0 q1 q2 q3 dqs q0 q1 cl=3 .0 co mma nd dq q0 q1 q2 q3 re ad ter m dqs wr it e d0 d1 d2 d3 d4 d5
integrated silicon solution, inc. www.issi.com 33 rev. 00d 03/19/08 is43r32800b burs tw ri te op erat io nc an be in te rrupt ed by wr it eo fa ny bank .r an do mc ol um na cce ss is al lo wed. writ et ow ri te in te rval is mi ni mu m1 cl k. w ri te inte rr upted by wr ite w ri te inte rr upte db yr ea d burs tw ri te op er at io nc an be in te rrupt ed by read of th es am eo rt he ot he rb an k. ra nd om co lu mn acces si sa ll ow ed .i nt erna lw ri te to re ad co mma nd in te rval (t wt r) is mi ni mu m1 cl k. th e i nputda ta on dq at th ei nt e rrupt in gr ea dc yc le is "d on 't care". tw tr is re fe re nc ed fr om th ef ir st po si ti ve edge af te rt he la st da ta in put . wr it ei nter ru pted by read (b l=8, cl=2 .5 ) co mma nd a0-7 ,9-1 1 a8 ba 0, 1 dq wr it e yi 0 00 re ad yj 0 00 da i0 da i1 qa j0 qa j1 qa j2 qa j3 qs qa j4 qa j5 qa j6 qa j7 dm tw tr /c lk cl k wr it ei nter ru pted by wr it e( bl =8 ) co mm an d a0-7 ,9-1 1 a8 ba 0, 1 wr it e yi 0 00 wr it e yk 0 10 wr it e yj 0 00 wr it e yl 0 00 dq da i1 da j1 da j3 da k1 da k3 da k5 da l1 dqs da l2 da l3 da l5 da l6 da l7 da l4 da l0 da k4 da k2 da k0 da i0 da j0 da j2 /c lk cl k
34 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b burs tw ri te op er at io nc an be in te rrupt ed by prec ha rg eo ft he sa me or al lb an k. ra nd om co lu mn acces si sa ll ow ed .t wr is re fe ren ced fr om th ef ir st po si ti ve cl ke dge af te rt he la st da ta in put . w ri te interr upted by pr ec ha rg e wr it ei nterr upted by p rech arge (b l=8, cl=2 .5) co mm an d a0-7 ,9-1 1 a8 ba 0, 1 dq wr it e yi 0 00 pr e 00 da i0 da i1 qs dm tw r /c lk cl k
integrated silicon solution, inc. www.issi.com 35 rev. 00d 03/19/08 is43r32800b i nitial iz ea nd mo de register se ts co mm an d /c lk cl k em rs pr e no p mr s pr e ar ar mr s ac t co de co de xa co de xa 10 xa a0-7 ,9-1 1 a8 co de 1 ba 0, 1 dqs dq 1 00 00 co de tm rd tm rd tr p tr fc tr fc tm rd mo de re gi st er se t, re se td ll ex te nd ed mo de re gi st er se t aut or efre sh si ng le cycl eo fa ut o -re fr es hi si ni ti ated wi th ar ef a( /cs=/r as =/ ca s= l, /w e= ck e= h) co mm an d. th er ef resh addr es si sg en erated in te rnally . 4096 re fa cy cl es wi th in 64 ms re fr es h 256mbi ts me mo ry ce ll s. th ea ut o- re fr es hi sp er fo rm ed on 4b an ks co nc u rre nt ly .b ef or ep er fo rm in g an au to re fr es h, al lb an ks mu st be in th ei dl es tate .a ut o- re fr es ht oa ut o -re fr es hi nt er va li sm in im um tr fc .a ny co mma nd mu st no tb es upp li ed to th ed ev ic eb ef or et rf cf ro mt he re fa co mma nd . auto-ref res h /r as ck e /c s /cas /w e a0-1 1 ba 0, 1 no po rd esel ec t tr fc au to ref resh on al lb an ks au to re fr es hona ll ba nk s /c lk cl k ck e in itia li ze an dm rs
36 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b s elf refresh se lf -ref re sh mo de is en te re db yi ss ui ng ar ef sc om ma nd (/cs=/ra s=/c as =l ,/ we =h,c ke =l ). on ce th es el f- re fr es hi si ni ti ated ,i ti sm ai nt ai ne da sl on ga sc ke is kept lo w. du ri ng th es el f- re fr es hm od e, ck ei sa sy nc hr onou sa nd th eo nl ye na bl ei nput ,a ll ot he ri n put si nc lu di ng cl ka re di sabl ed an di gnor ed ,s ot ha tp ower co ns um pt io n due to s ynchr onou si n put si ss av ed .t oe xi tt he se lf -re fr es h, supp ly in gs ta bl ec lk in put s, assert in gd esel or no pc o mma nd an dt he na sser ti ng ck ef or lo ng er th an tx snr/ tx srd. self -r efres h /r as ck e /c s /cas /w e a0-1 1 ba 0, 1 tx sn r se lf re fr es he xi t /c lk cl k xy xy tx sr d
integrated silicon solution, inc. www.issi.com 37 rev. 00d 03/19/08 is43r32800b th e purpo se of cl ks uspe nd is po we rd ow n. ck ei ss yn ch ro no us in put except dur in gt he se lf - re fr es hm od e. ac o mma nd at cycl ei si gnor ed .f ro mc ke =h to no rm al fu nc ti on ,d ll r eco ve ry ti me is not requ ir ed in th ec ondi ti on of th es ta bl ec lk op erat io n dur in gt he po we rd ow nm od e. p ow er down /c lk cl k po we rd ow nb yc ke co mma nd pr e ck e co mma nd ac t ck e st an db yp ow er do wn no p no p va li d no p no p va li d ac tiv ep ow er do wn dm is de fi ne da st he da ta ma sk fo rw ri te s. du ri ng wr it es ,d mm asks i nputda ta wo rd by wo rd .d m to wr it em as kl aten cy is 0. d mc ontrol dm f unction (b l=8, cl=2 ) co mm an d dq s dq dm wr it e re ad d0 d1 d3 d4 d5 d6 d7 ma sk ed by dm=h do n' tc ar e q2 q3 q4 q5 /c lk cl k q0 q1 q6 tx pnr /tx pr d
38 integrated silicon solution, inc. www.issi.com rev. 00d 03/19/08 is43r32800b frequency speed (ns) order part no. organization package 200 mhz 5 is43r32800b-5b 8mx32 144-ball fbga 200 mhz 5 is43r32800b-5bl 8mx32 144-ball fbga, lead-free 166 mhz 6 is43r32800b-6b 8mx32 144-ball fbga 166 mhz 6 is43r32800b-6bl 8mx32 144-ball fbga, lead-free 133 mhz 7.5 is43r32800b-75b 8mx32 144-ball fbga 133 mhz 7.5 is43r32800b-75bl 8mx32 144-ball fbga, lead-free ordering information - v d d = 2.5v commercial range: 0 o c to +70 o c frequency speed (ns) order part no. organization package 200 mhz 5 is43r32800b-5bi 8mx32 144-ball fbga 200 mhz 5 is43r32800b-5bli 8mx32 144-ball fbga, lead-free 166 mhz 6 is43r32800b-6bi 8mx32 144-ball fbga 166 mhz 6 is43r32800b-6bli 8mx32 144-ball fbga, lead-free 133 mhz 7.5 is43r32800b-75bi 8mx32 144-ball fbga 133 mhz 7.5 is43r32800b-75bli 8mx32 144-ball fbga, lead-free industrial range: -40 o c to +85 o c
integrated silicon solution, inc. www.issi.com 39 rev. 00d 03/19/08 is43r32800b mini ball grid array package code: b (144-ball) mbga - 12mm x 12mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 144 a 1.17 1.25 1.40 0.046 0.049 0.055 a1 0.32 0.35 0.38 0.013 0.014 0.015 d 11.95 12.00 12.05 0.470 0.472 0.474 d1 ? 8.80 ? ? 0.346 ? e 11.95 12.00 12.05 0.470 0.472 0.474 e1 ? 8.80 ? ? 0.346 ? e ? 0.80 ? ? 0.031 ? notes: 1. controlling dimensions are in millimeters. 2. 0.8 mm ball pitch 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m a b c d e f g h j k l m ? 0.45 +/? 0.05 (144x) d e e a1 seating plane a d1 e1 e 12 11 10 9 8 7 6 5 4 3 2 1

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